Adaptive body bias may be used after fabrication to improve a bin split in processors and to reduce a variation in frequency and leakage caused by process variations. In performing adaptive body bias, a unique body bias voltage may be set to maximize the frequency of the processor subject to leakage and total power constraints and the type of transistor technology in use. Body bias voltages may be applied to processors and other circuits that use P-type metal oxide semiconductor (PMOS) transistors, N-type metal oxide semiconductor (NMOS) transistors, or both.
Two types of body bias voltages may be used to control the frequency of a processor, namely forward body bias (FBB) voltages and reverse body bias (RBB) voltages. A forward body bias (FBB) voltage may reduce a threshold voltage of transistors, increase a drive current and increase circuit speed. At the same time, forward body bias may improve short-channel effects of the transistors. On the other hand, a reverse body bias (RBB) voltage may increase the threshold voltage, reduce the speed and also reduce the leakage current of the transistors. Body bias may therefore be used to control standby leakage of a processor while at a same time obtaining a maximum speed during active mode.
Body bias may be applied to either NMOS or PMOS transistors, or both. Applying body bias to NMOS transistors in a non-triple well process may present additional complexities since voltages lower than 0 volts may be required and the body of the NMOS devices (i.e., the p-substrates) may be shared among the transistors. Therefore, if a body bias higher than 0 volts is applied, any transistor coupled to a negative voltage may become forward biased by a large amount and may cause functionality and/or power consumption problems.
The circuitry for applying adaptive body bias may include two blocks, namely a central bias generator (CBG) and a local bias generator (LBG). The central bias generator may generate a reference voltage that is process, voltage and temperature independent. This voltage may represent the desired body bias to apply to NMOS and/or PMOS transistors in the processor core or other locations.
On the other hand, many local bias generators may be distributed throughout a processor die. The local bias generators may translate the reference voltage from the CBG into local block supply voltages and then drive these voltages to the transistors or other devices in each respective block. The translation may ensure that if a local block supply voltage changes, the body bias will change at substantially a same time so that a constant bias is maintained. For example, for NMOS body bias, the body voltage may track variations in a local block ground (Vss). On the other hand, for PMOS body bias, the body voltage may track variations in a local block voltage (Vcc). The LBGs may also provide drive strength to meet impedance requirements and minimize noise on transistor bodies.